-- 16进制共阴极7段数码显示译码器
------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity num_code is
    port(
        data_bcd : in std_logic_vector(3 downto 0),
        a, b, c, d, e, f, g : out std_logic
    );
end num_code;

architecture behave of num_code is
    signal num : std_logic_vector(3 downto 0);
    signal out_num : std_logic_vector(6 downto 0);
begin
    with data_bcd select
        out_num <= "1111110" when "0000",
                    "0110000" when "0001",
                    ...
                    ...
                    "1001111" when others;
    
    a <= out_num(6);
    b <= out_num(5);
    c <= out_num(4);
    d <= out_num(3);
    e <= out_num(2);
    f <= out_num(1);
    g <= out_num(0);
end behave;
